Semiconductor memory

ABSTRACT

A semiconductor memory comprises memory cells (15-18, 27-30), a data writing terminal (1), a data readout terminal (48), transistors (3-10, 35-42), address signal input terminals (23-26), subdecode signal input terminals (43-46), driving signal generating circuits (49-52), parallel readout circuits (79-82) and test mode switching signal input terminal (53, 88). In writing of function test data for the memory cells, the driving signal generating circuits turn all of the transistors (3-10) on in response to a test mode switching signal with no regard to address signals, thereby to simultaneously write data in the memory cells (15-18). Further, in readout of the function test data for the memory cells, the parallel readout circuits read the storage contents of the memory cells (27-30) storing the test data in response to a test mode switching signal with no regard to subdecode signals. Logic circuit means (90, 91, 94) may be provided to output logical value corresponding to the test data stored in the memory cells when all of the logical values of the test data are at the same level.

BACKGROUND OF THE INVENTION

The present invention relates to a semiconductor memory, and moreparticularly, it relates to a semiconductor memory, the feature of whichresides in the manner of writing and readout of test data in functiontests of a plurality of memory cells.

Description of the Prior Art

In a conventional semiconductor memory, function tests of memory cellsare performed in a wafer state of the semiconductor memory before thesame is packaged. Such function tests are executed by transmission andreception of signals between a memory testing device and thesemiconductor memory. For example, a prescribed logical value (e.g.,"0") is written in all of the memory cells forming the semiconductormemory by the memory testing device. Then, the storage contents of thememory cells are read bit by bit to detect whether or not the storagecontents match with the previously written logical values, thereby tomake decisions as to whether or not the memory cells function correctly.In the conventional semiconductor memory, writing and readout of testdata in and from the respective memory cells for such function tests areperformed through normal input/output circuits.

FIG. 1 is a schematic block diagram mainly showing electrical structureof an input (writing) circuit of a conventional semiconductor memory.

Description is now made on the structure of the semiconductor memory asshown in FIG. 1. In FIG. 1, input data W are supplied to a data inputbuffer 2 through a data writing terminal 1. In response to this, thedata input buffer 2 outputs the input data W and signals W obtained byinverting the input data W. The signals W outputted from the data inputbuffer 2 are supplied to one conducting terminal of each of transistors3, 5, 7 and 9, while the signals W outputted from the data input buffer2 are further supplied to one conducting terminal of each of transistors4, 6, 8 and 10. Outputs from respective other conducting terminals ofthe transistors 3 and 4 are amplified through a preamplifier 11, to becoupled with a 1-bit memory cell 15. In a similar manner, outputs fromrespective other conducting terminals of the transistors 5 and 6 areamplified through a preamplifier 12 to be coupled with a 1-bit memorycell 16 and outputs from the respective other conducting terminals ofthe transistors 7 and 8 are amplified through a preamplifier 13 to becoupled with a 1-bit memory cell 17 while outputs from respective otherconducting terminals of the transistors 9 and 10 are amplified through apreamplifier 14 to be coupled with a 1-bit memory cell 18. On offoperations of the transistors 3 and 4 are controlled by an output signalC₁ from a memory cell selecting circuit 19 and on off operations of thetransistors 5 and 6 are controlled by an output signal C₂ from a memorycell selecting circuit 20, while on off operations of the transistors 7and 8 are controlled by an output signal C₃ from a memory cell selectingcircuit 21 and on off operations of the transistors 9 and 10 arecontrolled by an output signal C₄ from a memory cell selecting circuit22. A terminal 23 receives an address signal A_(R) and a terminal 24receives an address signal A_(R) while a terminal 25 receives an addresssignal A_(C) and a terminal 26 receives an address signal A_(C), wherebyone of the memory cell selecting circuits 19 to 22 is selected to bedriven.

Description is now made on the data writing operation in the functiontests of the conventional semiconductor memory as shown in FIG. 1. Inthe data writing operation, the input data W are supplied to the datawriting terminal 1. The data input buffer 2 outputs a complementary pairof signals W and W. In order to make the signals W and W reach therespective memory cells to be written therein, the transistors 3 to 10must be in ON states. In the conventional semiconductor memory, a pairof transistors (for example, transistors 3 and 4) are turned on by oneof the memory cell selecting circuits designated by the address signalA_(R), A_(R), A_(C) or A_(C), whereby the data are written only in oneof the 1-bit memory cells (for example, memory cell 15). Then theaddress signals are changed so as to sequentially designate the othermemory cell selecting circuits and write the data in the respectivememory cells bit by bit in a sequential manner.

FIG. 2 is a schematic block diagram mainly showing electrical structureof an output (readout) circuit of the conventional semiconductor memory.

The structure of the semiconductor memory as shown in FIG. 2 is nowdescribed. In FIG. 2, storage contents of memory cells 27, 28, 29 and 30are read into corresponding preamplifiers 31 to 34. The preamplifiers 31to 34 respectively generate signals R₁ to R₄ obtained by invertingsignals R₁ to R₄ read from the memory cells 27 to 30, thereby to outputpairs of signals R₁ and R₁, R₂ and R₂, R₃ and R₃ and R₄ and R₄ which arein complementary relations each other respectively. The signalsoutputted from the preamplifiers 31 to 34 (hereinafter referred to asinternal output signals) are coupled in a line respectively throughconducting paths of transistors 35, 37, 39 and 41, to be supplied to oneinput terminal of a main amplifier 47 as a signal R. The internal outputsignals R₁ to R₄ are coupled in a line respectively through conductingpaths of transistors 36, 38, 40 and 42 to be supplied to the other inputterminal of the main amplifier 47. These input signals are amplified bythe main amplifier 47, to be supplied to an external output terminal 48as an external output signal.

Description is now made on the signal readout operation in the functiontest of the semiconductor memory as shown in FIG. 2.

In FIG. 2, it is assumed that logical values of "0" are previouslywritten by a memory testing device in all of the memory cells 27 to 30.The logical values of "0" stored in the respective memory cells 27 to 30are read into the preamplifiers 31 to 34, which in turn output thelogical values R₁ to R₄ ("0") read from the memory cells 27 to 30 andthe signals R₁ to R₄ ("1 ") being in complementary relations thereto asthe internal output signals. The internal output signal to be read atthe external output terminal 48 is selected among those outputted fromthe preamplifiers 31 to 34 by converting one of subdecode signalssupplied to subdecode signal input terminals 43 to 46 to a high level.For example, when a high-level subdecode signal is supplied only to theinput terminal 43, the transistors 35 and 36 alone are made conductiveso that the internal output signals R₁ and R₁ of the preamplifier 31 aresupplied to the main amplifier 47 as R and R to be amplified andoutputted from the external output terminal 48. In order to read theremaining internal output signals R₂ to R₄ and R₂ to R₄, the othersubdecode signals supplied to the other subdecode signal input terminals44, 45 and 46 may be sequentially converted into high levels. Thus, thelogical values for function tests written in the memory cells are readbit by bit at the external output terminal, thereby to individuallydecide the conditions of the respective memory cells.

In the conventional semiconductor memory as hereinabove described, sincethe test data must be written in a plurality of memory cells bit by bitand the storage contents of the plurality of memory cells must be readout bit by bit by utifizing normal input/output circuits, the time forthe function test per semiconductor memory is extremely prolongedbecause of mass storage of the semiconductor memory. On the other hand,it is known in the art to simultaneously test a plurality of bits byproviding on-chip test circuits such as retention test circuits andstress test circuits as disclosed in, for example, "A Programmable 256KCMOS EPROM with On-Chip Test Circuits" by S. Tanaka et al, 1984 IEEEInternational Solid-State Circuits Conference, pages 148 to 149, whereasno concept has yet been known as to simultaneous performance of writingand/or readout of function test data of a plurality of memory cells.

SUMMARY OF THE INVENTION

Briefly stated, the present invention provides a semiconductor memorywhich comprises a data writing terminal, n-bit memory cells (n: aninteger not less than 2) coupled in a parallel manner to the datawriting terminal, designating signal generating means for generatingsignals designating any one of the memory cells to be written with data,the number n of memory cell writing means each provided for respectiveones of the memory cells for receiving the memory cell designatingsignals to write the data in the designated memory cells and drivingsignal generating means for generating driving signals forsimultaneously driving all of the number n of memory cell writing meansin writing of data for the memory cell function tests.

According to another aspect of the present invention, the semiconductormemory comprises n-bit memory cells, the number n of internal outputsignal generating means each provided for respective ones of the memorycells for reading logical values held in the respective memory cells,signal selecting means for selecting one from the number n of logicalvalues outputted from respective ones of the internal output signalgenerating means, a data readout terminal for externally outputting thelogical value selected by the signal selecting means, a test data outputmeans connected to the number n of internal output signal generatingmeans for outputting memory cell function test data and a test modeswitching means for activating the test data output means only inreadout of the data for the memory cell function tests.

According to still another aspect of the present invention, thesemiconductor memory comprises a data writing terminal, n-bit memorycells coupled in parallel with the data writing terminal, a designatingsignal generating means for generating signals designating any one ofthe memory cells to be written with data, the number n of memory cellwriting means each provided for respective one of the memory cells forreceiving the memory cell designating signals thereby to write data inthe designated memory cells, driving signal generating means forgenerating driving signals for simultaneously driving all of the numbern of memory cell writing means in writing of data for the memory cellfunction tests, the number n of internal output signal generating meanseach provided for respective ones of the memory cells to read logicalvalues held in the respective memory cells, signal selecting means forselecting one from the number n of logical values outputted from therespective internal output signal generating means, a data readoutterminal for externally outputting the logical value selected by thesignal selecting means, a test data output means connected to the numbern of internal output signal generating means to output memory cellfunction test data and a test mode switching means for activating thetest data output means only in readout of the memory cell function testdata.

According to a further aspect of the present invention, the test dataoutput means are implemented by the number n of parallel readout meansfor directly outputting the number n of logical values outputted fromthe number n of internal output signal generating means in a parallelmanner.

According to a still further aspect of the present invention, the testdata output means is implemented by logic circuit means which outputs,when all of the number n of logical values outputted from the number nof internal output signal generating means are at the same level, thesaid logical value.

Accordingly, a principal object of the present invention is to provide asemiconductor memory which can remarkably reduce the time for functiontests of memory cells.

A principal advantage of the present invention is that a plurality ofmemory cell writing means are simultaneously driven in writing of memorycell function test data thereby to simultaneously write the same testdata in the plurality of memory cells.

Another advantage of the present invention is that the storage contentsof a plurality of memory cells can be simultaneously read in readout ofmemory cell function test data.

Still another advantage of the present invention is that the storagecontents of a plurality of bits (n bits) of memory cells are externallyoutputted in a parallel manner thereby to perform function tests of theplurality of bits of memory cells in a parallel manner, whereby the timefor reading the memory cells in the function tests can be reduced to 1/nof that of the conventional memory per bit.

A further advantage of the present invention is that a plurality of bits(n bits) of memory cells can be simultaneously subjected to functiontests by externally outputting, when all of the logical values read fromthe plurality of bits of memory cells are at the same level, the saidlogical value, whereby the time for testing the memory cells can bereduced to 1/n of that in the conventional memory per bit.

The above and other objects, features, aspects and advantages of thepresent invention will become more apparent from the following detaileddescription of the present invention when taken in conjunction with theaccompanying drawings.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a schematic block diagram showing electrical structure of awriting circuit of a conventional semiconductor memory;

FIG. 2 is a schematic block diagram showing electrical structure of areadout circuit of the conventional semiconductor memory;

FIG. 3 is a schematic block diagram showing a semiconductor memoryaccording to an embodiment of the present invention;

FIGS. 4 and 5 are circuit diagrams showing driving signal generatingcircuits forming the embodiment of the present invention;

FIG. 6 is a schematic block diagram showing a semiconductor memoryaccording to a second embodiment of the present invention;

FIGS. 7A and 7B are waveform diagrams for illustrating the operations ofthe semiconductor memory as shown in FIG. 6;

FIG. 8 is a schematic block diagram showing a semiconductor memoryaccording to a third embodiment of the present invention;

FIG. 9 is a circuit diagram showing an AND gate forming thesemiconductor memory as shown in FIG. 8 in detail;

FIGS. 10A.to 10D are waveform diagrams for illustrating the operationsof the circuit as shown in FIG. 9;

FIG. 11 is a circuit diagram showing a main amplifier forming thesemiconductor memory as shown in FIG. 8; and

FIGS. 12A to 12D are waveform diagrams for illustrating the operationsof the circuit as shown in FIG. 11.

DESCRIPTION OF THE PREFERRED EMBODIMENTS

FIG. 3 is a schematic block diagram showing electrical structure of awriting circuit of a semiconductor memory according to an embodiment ofthe present invention.

The structure of the embodiment as shown in FIG. 3 is identical to thatof the conventional semiconductor memory as shown in FIG. 1, except forthe following points: Driving signal generating circuits 49 to 52 areprovided in place of the memory cell selecting circuits 19 to 22 and atest mode switching signal (TM signal) input terminal 53 is adapted tosupply the TM signal to the respective driving signal generatingcircuits 49 to 52.

The operation of the embodiment as shown in FIG. 3 is now described. TheTM signal rises at high level in a test mode, and in a mode (hereinafterreferred to as normal mode) other than the test mode, i.e., when the TMsignal is at low level, the respective driving signal generatingcircuits 49 to 52 operate in a similar manner to the memory cellselecting circuits 19 to 22 as shown in FIG. 1. Namely, when the TMsignal is at low level, one of the driving signal generating circuitsselected by address signals A_(R), A_(R), A_(C) and A_(C) operates tocontrol a pair of transistors related thereto to enter ON states,thereby to write input data in one of the memory cells designated by theaforementioned address signals in conventional procedure.

On the other hand, in the test mode, i.e., when the TM signal rises athigh level, all of the driving signal generating circuits 49 to 52simultaneously output signals C₁ to C₄ for driving related pairs of thetransistors to enter ON states respectively, regardless of the addresssignals. In other words, when the TM signal is at high level, all oftransistors 3 to 10 enter ON states, whereby output signals W and W froma data input buffer 2 are written in all of memory cells 15 to 18.

The driving signal generating circuits 49 to 52 are all in the samecircuit structure, and FIG. 4 shows a detailed circuit diagram thereofwith respect to the driving signal generating circuit 49, which is takenhere as an example for illustration.

Description is now made on the structure of the driving signalgenerating circuit 49 as shown in FIG. 4. The circuit as shown in FIG. 4is mainly formed by a driving signal generating portion 54, a memorycell selecting portion 55 and a latch circuit 56. A terminal 57 receivesthe TM signal from a terminal 53 as shown in FIG. 3. The TM signal issupplied to the control terminal of a transistor 59 through a transistor58.

On the other hand, both of terminals 60 and 61 receive low-level signalswhen the address signals A_(R) and A_(C) are adapted to select thedriving signal generating circuit 49. In this case, transistors 62 and63 enter OFF states. A terminal 64 receives basic clock signals φ fordeciding the timing for memory cell writing. A transistor 65 is on offcontrolled by the clock signals φ, while one conducting terminal thereofis coupled to transistors 62, 63 and 66. The other conducting terminalof the transistor 66 is coupled with the control terminal of atransistor 67. Terminals 68, 69, 70 and 71 receive high-level signals.The latch circuit 56 is formed by a terminal 72 for supplying high-levelsignals, a terminal 73 receiving the aforementioned basic clock signalsφ and transistors 74 and 75, to be controlled by the clock signals φ,thereby to previously make a terminal 76 at a low level.

The operation of the circuit as shown in FIG. 4 is now described. In thenormal mode, i.e., when the TM signal is at low level, the transistor 59enters an OFF state. When the memory cell selecting portion 55 in placefunctions as a normal memory selecting circuit and the driving signalgenerating circuit 49 is selected by the address signals, thetransistors 62 and 63 both enter OFF states and high-level signal issupplied to the control terminal of the transistor 67 in accordance withthe clock signals φ, whereby the transistor 67 enters an ON state. Inresponse to this, the terminal 76 outputs the high-level signal C₁,thereby to make the related transistors 3 and 4 enter ON states.

On the other hand, in the test mode, i.e., during the period when the TMsignal is at high level, the transistor 59 is continuously in an ONstate, so that the high-level signal C₁ is continuously outputted at theterminal 76 to make the related transistors 3 and 4 enter ON statesregardless of the address signals.

FIG. 5 is a circuit diagram showing a driving signal generating circuitwhich makes related transistors enter ON states only when the writingoperation to the memory cells is further performed in the aforementionedtest mode. In FIG. 5, signals φ_(W) are converted into high levels whenwriting is actually made in the memory cells in the test mode. Thestructure of the circuit diagram as shown in FIG. 5 is identical to thatof the circuit diagram as shown in FIG. 4 except for the followingpoints: The signals φ_(W) are supplied to one conducting terminal of atransistor 58 through a terminal 57, while the control terminal of atransistor 58 receives TM signal through a terminal 78. Thus, a terminal76 outputs driving signals C₁ only when both of the TM signal and thesignals φ_(W) are at high level, thereby to make the related transistors3 and 4 enter ON states.

Therefore, according to this embodiment, the same test data can besimultaneously written in a plurality of memory cells in the functiontests thereof.

FIG. 6 is a schematic block diagram showing electrical structure of areadout circuit of a semiconductor memory according to a secondembodiment of the present invention.

The structure of the embodiment as shown in FIG. 6 is the same as thatof the conventional semiconductor memory as shown in FIG. 2 except forthe following points: Namely, parallel readout circuits 79 to 82 areprovided in correspondence to respective ones of preamplifiers 31 to 34.The parallel readout circuits 79 to 82 are in the same structure, anddetailed description is now made on the parallel readout circuit 79which is taken as an example for illustration. Internal output signal R₁of the preamplifier 31 is coupled to the control terminal of atransistor 85 through a transistor 83 forming the parallel readoutcircuit 79. In a similar manner, internal output signal R₁ of thepreamplifier 31 is supplied to the control terminal of a transistor 86through a transistor 84. The control terminals of the transistors 83 and84 are coupled to an input terminal 88 for test mode switching signalgenerated by a memory testing device and converted into high levels inthe test mode. Further, one conducting terminal of each transistors 85and 86 are coupled with each other to form a parallel external outputterminal 87, while the other conducting terminal of the transistor 85 isconnected to a voltage supply terminal 89 for supplying prescribedvoltage which is generated by the memory test unit and rises in readoutof parallel signals, and the other conducting terminal of the transistor86 is grounded.

FIGS. 7A and 7B are waveform diagrams for illustrating the operations ofthe second embodiment as shown in FIG. 6.

Description is now made on the operations of the second embodiment ofthe present invention with reference to FIGS. 7A and 7B.

In order to perform function tests of the memory cells, logical valuesof "0" are written in all of the memory cells by a memory testing device(not shown). If the respective memory cells function correctly, thelogical values of "0" will be read from the same while those are decidedas defective if no "0" output is obtained. Assuming that the respectivememory cells function correctly in the embodiment as shown in FIG. 6,the internal output signals R₁ to R₄ read by the preamplifiers 31 to 34become "0" and the complementary signals R₁ to R₄ thereof will become"1". The operation of the parallel readout circuit 79 is now describedparticularly with respect to the case of R₁ ="0" and R₁ ="1". As shownat (1) and (2) in FIG. 7A, the preamplifier 31 outputs the internaloutput signals R₁ and R₁ after the time t₁. In other words, the signalR.sub. 1 is equal to "0" or at low level and the signal R₁ is equal to"1" or at high level after the time t₁, as hereinabove described. SymbolTM as shown at (3) in FIG. 7A indicates the aforementioned test modeswitching signal, which is maintained at high level in the test mode.Namely, the transistors 83 and 84 enter conductive states in the testmode, whereby the internal output signals R₁ and R₁ are supplied to themain amplifier 47 through conventional signal selecting means as well asto the control terminals of the transistor 85 and 86 through thetransistors 83 and 84, respectively. Symbol φ at (4) in FIG. 7Aindicates a signal supplied to the terminal 89 for determining thetiming for reading the parallel signals as hereinabove described, whichis converted into high level after the time t₂ to supply prescribedvoltage. This signal φ is supplied to one conducting terminal of thetransistor 85 from the input terminal 89. In this state, the controlinput of the transistor 85, i.e., R₁ is at low level and the controlinput of the transistor 86, i.e., R₁ is at high level, and hence thetransistor 85 is in an OFF state while the transistor 86 is in an ONstate. In other words, a low level signal is outputted at the parallelexternal output terminal 87 in this state.

FIG. 7B is a waveform diagram for illustrating the operation in the casewhere logical values of "1" are written in all of the memory cellscontrary to the case of FIG. 7A. In this case, the signal R₁ is at highlevel and the signal R₁ is at low level as shown at (1) and (2) in FIG.7B, and hence the transistor 85 is in an ON state while the transistor86 is in an OFF state. Namely, a high level signal is outputted at theparallel external output terminal 28 as shown at (5) in FIG. 7B. Asobvious from FIGS. 7A and 7B, the signal "0" is directly outputted atthe parallel external output terminal 87 when the values of "0" are heldin the memory cells while the signal "1" is outputted at the same whenthe values of "1" are held in the memory cells. All of the parallelreadout circuits 79 to 82 are in the same circuit structure, and hencethe respective parallel readout circuits perform the same operation asthat described above with reference to FIGS. 7A and 7B. Thus, thestorage contents of the respective memory cells are externally outputtedin a parallel manner through corresponding ones of the parallel readoutcircuits.

The aforementioned function tests of the memory cells are performed in awafer state of the semiconductor memory before the same is packaged, andthe test mode switching signal input terminal 88 may be grounded to beat a low level when the memory is packaged after the function tests, sothat only a normal readout circuit functions thereafter.

Thus, function tests of a plurality of bits of memory cells can besimultaneously performed according to the second embodiment.

FIG. 8 is a schematic block diagram showing electrical structure of asemiconductor memory according to a third embodiment of the presentinvention.

The structure of the embodiment as shown in FIG. 8 is identical to thatof the conventional semiconductor memory as shown in FIG. 2 except forthe following points:

The semiconductor memory as shown in FIG. 8 is provided with an AND gate90 which receives internal output signals R₁ to R₄ outputted fromrespective ones of preamplifiers 31 to 34, an AND gate 91 which receivessignals to R₁ to R₄ and an output circuit 94 which is formed by atransistor 92 having a control terminal coupled to the output of the ANDgate 90 and a transistor 93 having a control terminal coupled to theoutput of the AND gate 91. In further detail, one conducting terminal ofeach of transistors 92 and 93 is coupled to form a testing externaloutput terminal 95, while the other conducting terminal of thetransistor 92 is coupled to a terminal 96 for supplying a signal at ahigh level and prescribed voltage in the function tests of memory cellsand the other conducting terminal of the transistor 93 is grounded.

Description is now made on the operation of the third embodiment asshown in FIG. 8.

In the memory cell function tests, for example, logical values of "0"are written in all of the memory cells by a memory testing device (notshown). If the respective memory cells function correctly, the writtenvalues of "0" will be directly read from the memory cells, while if "1"output is included the corresponding memory cell is decided asdefective. Assuming that the respective memory cells function correctlyin the embodiment as shown in FIG. 8, the internal output signals R₁ toR₄ read by the respective preamplifiers 31 to 34 become "0", which isequal to the previously written logical values, and the complementarysignals to R₁ to R₄ become "1".

As shown in FIG. 8, the AND gate 90 outputs an AND signal R' of the fourinternal output signals R₁ to R₄ while the AND gate 91 outputs an ANDsignal R' of the four internal output signals R₁ to R₄. In other words,the output R' from the AND gate 90 is "1" only when all of the signalsR₁ to R₄ are at the level "1", and it becomes "0" in other case. Theoutput R' from the AND gate 91 is "1" only when all of the signals R₁ toR₄ are at the level "1", and it becomes "0" in other case. The output R'from AND gate 91 is "1" only when all of the signals RHD 1 to R₄ are atthe level "1", and it becomes "0" in other case.

Namely, when all of the signals R₁ to R₄ are at the level "1", all ofthe internal output signals in complementary relation thereto become"0", and hence R'="1" and R'="0" in this case.

On the other hand, when all of the signals R₁ to R₄ are at the level"0", all of the internal output signals R₁ to R₄ in complementaryrelation thereto become "1", and hence R'="0" and R'="1" in this case.

In other case, i.e., when the signals R₁ to R₄ include both of "0" and"1", the signals R₁ to R₄ also include both of "0" and "1", and both ofthe outputs R' and R' become "0" in this case.

In the aforementioned case of R'="1" and R'"0", the transistor 92 entersan ON state and the transistor 93 enters an OFF state. A high-levelsignal is supplied to a terminal 96, whereby "1" is outputted at atesting external output terminal 95. Namely, in the case where all ofthe signals R₁ to R₄ are at the level "1", the same logical value "1" isoutputted from the testing external output terminal 95.

In the case of R'="0" and R'="1", the transistor 92 is turned off andthe transistor 93 is turned on. One conducting terminal of thetransistor 93 is grounded (connected at a low level), and "0" isoutputted at the testing external output terminal 95. Namely, in thecase where all of the signals R₁ to R₄ are at the level "0", the samelogical value "0" is outputted from the testing external output terminal95.

Further, in the case of R'="0" and R'="0", both of the transistors 92and 93 are turned off so that the testing external output terminal 95enters a high-impedance state. Therefore, when the signals R₁ to R₄include both of "0" and "1", i.e., when 4-bit memory cells correspondingto the internal output signals R₁ to R₄ include that which functionsincorrectly, no output appears at the testing external output terminal95.

FIG. 9 illustrates details of the AND gates 90 and 91 as shown in FIG. 8and various circuits related thereto, which are not shown in FIG. 8.

The structure of the circuit as shown in FIG. 9 is now described. Thecircuit as shown in FIG. 9 is mainly formed by the AND gates 90 and 91,a clock signal generating circuit 97 and latch circuits 98 and 99.Respective ones of four input terminals 100 to 103 of the AND gate 90are supplied with the internal output signals R₁ to R₄ from thepreamplifiers 31 to 34. A terminal 104 is supplied with a high-levelsignal, and transistors 105, 106, 107 and 108 are in ON states. Namely,the internal output signals R₁ to R₄ are supplied to the controlterminals of transistors 109, 110, 111 and 112. On the other hand,respective ones of four input terminals 113 to 116 of the AND gate 91are supplied with the internal output signals R₁ to R₄ to from thepreamplifiers 31 to 34. A terminal 117 is supplied with a high-levelsignal, and transistors 118, 119, 120 and 121 are in ON states. Namely,the internal output signals R₁ to R₄ are supplied to the controlterminals of transistors 122, 123, 124 and 125.

The clock signal generating circuit 97 is formed by transistors 126 and127. The control terminal of the transistor 126 continuously receivesbasic clock signals φ₁ ' through an input terminal 128, while oneconducting terminal of the transistor 126 receives a test mode switchingsignal TM, which is converted into a high level in function tests, froma memory testing device (not shown) provided in the exterior through aninput terminal 129. The control terminal of the transistor 127 receivesa signal TM obtained by inverting the test mode switching signal TMthrough an input terminal 130, while one conducting terminal of thetransistor 127 is grounded. Respective other conducting terminals of thetransistors 126 and 127 are coupled with each other so as to supply aninput clock signal φ₁ to the conducting terminals of the transistors 109and 122 of the AND gates 90 and 91.

The output of the AND gate 90, i.e., one conducting terminal of thetransistor 112 is coupled to the latch circuit 98. The latch circuit 98is adapted to previously make the signal R' in a "0" state by a clocksignal φ₂ supplied to a terminal 131 which falls in a low level inadvance to the rise of the clock signal φ₁. The latch circuit 99 is alsoadapted to previously make the signal R' in a "0" state at the timing ofthe clock signal φ₂ supplied to a terminal 132. Finally, the AND outputR' of the AND gate 90 is supplied to a terminal 133 while the AND outputR' of the AND gate 91 is supplied to a terminal 134.

FIGS. 10A to 10D are waveform diagrams for illustrating the operationsof the circuit as shown in FIG. 9.

Description is now made on the operation of the circuit as shown in FIG.9 with reference to FIGS. 10A to 10D. FIG. 10A shows the operation in anormal state (hereinafter referred to as normal mode) other than a testmode. A test mode switching signal TM supplied to the terminal 129 ofthe clock signal generating circuit 97 from the memory testing deviceprovided in the exterior is at a low level (L) as shown at (1) in FIG.10A. The signal TM obtained by inverting the signal TM is at a highlevel (H) as shown at (5) in FIG. 10A, whereby the transistor 127 entersan ON state. Therefore, if the basic clock signal φ₁ ' rises as shown at(2) in FIG. 10A, the signal φ₁ continuously remains at a low level. Whenthe signal φ₂ is at a high level as shown at (4) in FIG. 10A, the latchcircuits 98 and 99 so operate that the signals R' and R' are maintainedat low levels as shown at (6) and (7) in FIG. 10A. However, the signalφ₁ continuously remains at a low level even after the signal φ₂ falls ina low level as shown at (4), and hence both of the signals R' and R' areconverted into low levels, i.e., "0" as shown at (6) and (7) in FIG. 10Awith no regard to the internal output signals R₁ to R₄ and R₁ to R₄.Thus, no output appears at the testing external output terminal 95 asshown in FIG. 8 in the normal mode.

FIG. 10B shows the operation in the test mode, particularly in the casewhere the signals R₁ to R₄ are at the level "1". In this case, the TMsignal is continuously at a high level as shown at (1) in FIG. 10B andthe TM signal is continuously at a low level as shown at (5), and hencethe transistor 127 is continuously in an OFF state. Therefore, as shownat (2) and (3) in FIG. 10B, the clock signal φ₁ rises simultaneouslywith the rise of the basic clock signal φ₁ '. While the latch circuits98 and 99 operate by the clock signal φ₂ as shown at (4), both of thesignals R' and R' are maintained at low levels. However, after the clocksignal φ₂ falls in a low level, all of the transistors 109 to 112 enterON states since all of the signals R₁ to R₄ are at the level "1", andhence the high-level clock signal φ₁ is outputted at R' whereby R'="1"as shown at (6). When all of the signals R₁ to R₄ are at the level "1",R₁ to R₄ are all "0" and hence all of the transistors 122 to 125 enterOFF states so that the signal R' become "0" of a low level. Thus, asignal of "1" is outputted at the testing external output terminal 95 asshown in FIG. 8 in the test mode.

FIG. 10C also shows the operation in the test mode, particularly in thecase where the signals R₁ to R₄ are at the level "0". The TM signal iscontinuously at a high level as shown at (1) in FIG. 10C and TM signalis at a low level as shown at (5), and hence the transistor 127 iscontinuously in an OFF state. Therefore, as shown at (2) and (3) in FIG.10C, the clock signal φ₁ rises simultaneously with the rise of the basicclock signal φ₁ '. While the latch circuits 98 and 99 operate by theclock signal φ₂ as shown at (4), the signals R' and R' are at low levelsas shown at (6) and (7). However, after the clock signal φ₂ falls in alow level as shown at (4), all of the transistors 109 to 112 enter OFFstates since all of the signals R₁ to R₄ are at the level "0", and hencethe output at R' is "0" of a low level. On the other hand, when all ofthe signals R₁ to R₄ are at the level "0", the signals R₁ to R₄ are allat the level "1", and hence all of the transistors 122 to 125 enter ONstates whereby the clock signal φ₁ of a high level is outputted at R' sothat R'="1". Thus, a signal of "0" is outputted at the testing externaloutput terminal 95 as shown in FIG. 8 in the test mode.

FIG. 10D also shows the operation in the test mode, particularly in thecase where the signals R₁ to R₄ include "0" and "1". The TM signal iscontinuously at a high level as shown at (1) in FIG. 10D while the TMsignal is continuously at a low level as shown at (5), and hence thetransistor 127 is continuously in an OFF state. Therefore, as shown at(2) and (3) in FIG. 10D, the clock signal φ₁ rises simultaneously withthe rise of the basic clock signal φ₁ '. While the latch circuits 98 and99 operate by the clock signal φ₂ as shown at (4), the signals R' and R'are at low levels as shown at (6) and (7). After the clock signal φ₂falls in a low level as shown at (4), any of the transistors 109 to 112enters an OFF state since any one of the signals R₁ to R₄ is "0",whereby the output R' is "0" of a low level as shown at (6). On theother hand, one of the transistors 122 to 125 enters an OFF state sinceone of the signals R₁ to R₄ is "0", and hence the output R' is "0" of alow level as shown at (7). Thus, the testing external output terminal 95as shown in FIG. 8 enters a high-impedance state, whereby no outputappears at the same in the test mode.

The output circuit 94 as shown in FIG. 8 may be assembled into the mainamplifier 48 so as to select either the external output in the normalmode or the testing external output of the test mode outputted from thetesting external output terminal 95 in the embodiment as shown in FIG. 8and output the same from an external output terminal 48 by switching thetest mode switching signal TM.

FIG. 11 is a circuit diagram showing a main amplifier 47 also serving asthe aforementioned testing external output circuit. Description is nowmade on the structure of the circuit as shown in FIG. 11.

A terminal 135 receives an internal signal R selected by a normalsubdecode signal while a terminal 136 receives an internal signal R alsoselected by a subdecode signal. Terminals 137 and 138 receive the outputR' from an AND gate 90, while terminals 139 and 140 receive the outputR' from an AND gate 91. A terminal 141 receives a TM signal obtained byinverting a TM signal and a terminal 142 receives a signal φ₄ foractivating the entire main amplifier 47 while a terminal 143 receives anequalizing signal φ₅ in advance of activation of the main amplifier 47and a terminal 144 also receives an equalizing signal φ₆. Transistors145 and 146 are adapted to function as circuits for generating a signalφ₇ for converting nodes N₁ and N₂ into low levels before the entire mainamplifier 47 is activated by the signal φ₄ only in a test mode. Thesignal R supplied to the terminal 135 is coupled to the control terminalof a transistor 148 which is coupled to the activating signal φ₄ througha transistor 147 which is controlled by the TM signal. The signal Rsupplied to the terminal 136 is coupled to the control terminal of atransistor 150 which is coupled to the activating signal φ₄ through atransistor 149 which is controlled by the TM signal. Further, oneconducting terminal of the transistor 148 is coupled to the controlterminal of a transistor 151 forming the output circuit while oneconducting terminal of a transistor 150 is coupled to the controlterminal of a transistor 152 also forming the output circuit. The signalR' received by the terminal 137 is supplied to the control terminal of atransistor 153, and a high level signal of prescribed voltage suppliedfrom a terminal 154 is coupled to the control terminal of the transistor148 through the transistor 153. The signal R' received by the terminal139 is supplied to the control terminal of a transistor 155, while ahigh level signal of prescribed voltage supplied from a terminal 156 iscoupled to the control terminal of the transistor 150 through thetransistor 155. When the TM signal is at a high level in the test mode,the transistor 146 is turned off so that a basic clock signal φ₇ ' isoutputted as an inpul clock signal φ₇ from one conducting terminal ofthe transistor 145, to be supplied to the control terminals oftransistors 157 and 158. Further, the signal R' received by the terminal140 is coupled to the control terminal of a transistor 159, while thesignal R' received by the terminal 138 is coupled to the controlterminal of a transistor 160.

A high level signal is supplied to a terminal 161, and when the controlterminals of the transistors 151 and 152 receive signals of high and lowlevels respectively, a high level signal "1" is outputted at an externaloutput terminal 48, and a low level signal "0" is outputted at theexternal output terminal 48 when the control terminals of thetransistors 151 and 152 receive signals of low and high levels,respectively, while the external output terminal 48 enters ahigh-impedance state (open state) when both of the control terminals ofthe transistors 151 and 152 receive signals of a low level.

FIGS. 12A to 12D are waveform diagrams for illustrating the operationsof the circuit as shown in FIG. 11.

Referring now to FIGS. 12A to 12D, description is made on the operationsof the circuit as shown in FIG. 11. FIG. 12A shows the operation in thenormal mode, in which the TM signal is at a low level and the TM signalis at a high level whereby the transistors 147 and 149 enter ON states.Therefore, the signals R and R are supplied to the control terminals ofthe transistors 148 and 150. When the signal φ₄ rises at a high level atthe timing as shown at (5), the signal R received by the controlterminal of the transistor 148 is thereafter supplied to the controlterminal of the transistor 151 while the signal R received by thecontrol terminal of the transistor 150 is supplied to the controlterminal of the transistor 152, so that the external output terminal 48outputs a signal of the normal mode as shown at (10).

FIG. 12B is a waveform diagram for illustrating the operation in thetest mode particularly in the case where R'="1" (R₁ to R₄ ="1") andR'="0" (R₁ to R₄ ="0"). In this case, the TM signal is at a high leveland the TM signal is at a low level, whereby the transistors 147 and 149enter OFF states. When the signal φ₄ rises at a high level at the timingshown at (5), the signal R' received by the control terminal of thetransistor 153 is thereafter supplied to the control terminal of thetransistor 151 while the signal R' received by the control terminal ofthe transistor 155 is supplied to the control terminal of the transistor152, so that the external output terminal 48 outputs the logical value"1" which is equal to those of the signals R₁ to R₄ as shown at (10).

FIG. 12C is a waveform diagram for illustrating the operation in thetest mode particularly in case where R'="0" (R₁ to R₄ ="0") and R₁="1"(R₁ to R₄ ="1"). The TM signal is at a high level and the TM signalis at a low level, whereby the transistors 147 and 149 enter OFF states.When the signal φ₄ rises at a high level at the timing shown at (5), thesignal R' received by the control terminal of the transistor 153 isthereafter supplied to the control terminal of the transistor 151 whilethe signal R' received by the control terminal of the transistor 155 issupplied to the control terminal of the transistor 152, whereby theexternal output terminal 48 outputs the logical value "0" which is equalto those of R₁ to R₄ as shown at (10).

FIG. 12D is a waveform diagram for illustrating the operation in thetest mode particularly in case where R'="0" (R₁ to R₄ include "0" and"1") and R'="0" (R₁ to R₄ include "0" and "1"). In this case, the TMsignal is at a high level and the TM signal is at a low level wherebythe transistors 147 and 149 enter OFF states. When the signal φ₄ risesat a high level at the timing shown at (5), the signal R' received bythe control terminal of the transistor 153 is thereafter supplied to thecontrol terminal of the transistor 151 while the signal R' received bythe control terminal of the transistor 155 is supplied to the controlterminal of the transistor 152, whereby the external output terminal 48enters a high-impedance state as shown at (10).

As hereinabove described, the storage contents of the 4-bit memory cellsare unified to an AND output signal (4-bit degenerate signal) byemploying AND gates, thereby to enable a decision that the logicalvalues outputted from the external output terminal are stored in all ofthe 4-bit memory cells. If the logical values are equal to thosepreviously written in the memory cells for the function tests, all ofthe 4-bit memory cells can be considered to function correctly. When nological value is outputted, i.e., when the external output terminal isin a high-impedance state, it is recognized that the 4-bit memory cellsinclude those storing "0" and those storing "1" and at least one of thememory cells is defective.

When it is necessary to further specify the defective cell included inthe 4-bit memory cells, the test mode may be switched to the normal modeto sequentially read the group of 4-bit memory cells including thedefective cell by a general readout means to make decisions bit by bit.

Although the above description of the respective embodiments has beenmade with respect to a semiconductor memory in which data are written in4-bit memory cells from one data writing terminal and that in whichstorage contents from 4-bit memory cells are read at an external outputterminal, the number of bits is not restricted to four and thesemiconductor memory may be implemented in any desired type such as adynamic type semiconductor device.

Further, the plurality of bits of simultaneous writing means accordingto the first embodiment and the plurality of bits of simultaneouswriting means according to the second or third embodiment may beassociated with each other to further reduce the test time.

Although the present invention has been described and illustrated indetail, it is clearly understood that the same is by way of illustrationand example only and is not to be taken by way of limitation, the spiritand scope of the present invention being limited only by the terms ofthe appended claims.

What is claimed is:
 1. A semiconductor memory comprising:a data writingterminal; n-bit memory cells coupled in parallel to said data writingterminal, n being an integer not less than 2; designating signalgenerating means for generating memory cell designating signals fordesignating any one of said n-bit memory cells to be written with data;memory cell writing means of said number n each provided for respectiveones of said n-bit memory cells for receiving said memory celldesignating signals respectively from said designating signal generatingmeans thereby to write data in designated memory cells; and drivingsignal generating means operative during a memory test mode of operationof said memory for generating driving signals for simultaneously drivingall of said memory cell writing means of said number n to write memoryfunction test data in said memory cells.
 2. A semiconductor memory inaccordance with claim 1, whereinsaid driving signal generating meanshave switching means switched in response to control signals from anexternal source of control signals to supply said driving signals tosaid memory cell writing means of said number n when memory functiontest data are being written in said memory cells and to supply saidmemory cell designating signals to said memory cell writing means ofsaid number n when memory function test data are not being written insaid memory cells.
 3. A semiconductor memory in accordance with claim 1,whereinsaid driving signal generating means are provided with timingsignal generating means for generating timing signals to which datawriting in said data writing terminal in synchronized, while generatingsaid driving signals in response to said timing signals.
 4. Asemiconductor memory comprising:n-bit memory cells, n being an integernot less than 2; internal output signal generating means of said numbern each provided for respective ones of said n-bit memory cells forreading logical values held in respective said n-bit memory cells tooutput the same; signal selecting means for selecting one value fromsaid logical values of said number n outputted from respective ones ofsaid internal output signal generating means of said number n; a datareading terminal for externally outputting said one logical valueselected by said signal selecting means; test data output meansconnected to said internal output signal generating means of said numbern for outputting data from said internal output signal generating meansas memory cell function test data; and test mode switching meansresponsive to a memory function test mode of operation of the memory foractivating said test data output means only in readout of said memorycell function test data.
 5. A semiconductor memory in accordance withclaim 4, whereinsaid test data output means are implemented by parallelreadout means of said number n for directly outputting said logicalvalues of said number n outputted from said internal output signalgenerating means of said number n in a parallel manner.
 6. Asemiconductor memory in accordance with claim 5, whereinsaid internaloutput signal generating means respectively output logical values incomplementary relation to said logical values read from said memorycells, respective one of said parallel readout means of said number ncomprising: an output terminal, a first signal source for supplyinghigh-level signals, a second signal source for supplying low-levelsignals, first switching means having a control terminal connected tosaid internal output signal generating means for receiving said logicalvalue held in said memory cell, a first conducting terminal connected tosaid output terminal, and second switching means having a controlterminal connected to said internal output signal generating means forreceiving said logical value in said complementary relation, a firstconducting terminal connected to said second signal source and a secondconducting terminal connected to said output terminal, and said testmode switching means comprising: third switching means for receiving acontrol signal from an external source of control signals in saidreadout of said memory cell function test data thereby to makecontinuity between said internal output signal generating means and saidcontrol terminal of said first swtiching means, and fourth switchingmeans for receiving said control signal from the external source ofcontrol signals in said readout of said memory cell function test datathereby to make continuity between said internal output signalgenerating means and said control terminal of said second switchingmeans.
 7. A semiconductor memory in accordance with claim 4, whereinsaidtest data output means is implemented by logic circuit means whichoutputs corresponding logical value when all of said logical values ofsaid number n outputted from said internal output signal generatingmeans of said number n are at the same level.
 8. A semiconductor memoryin accordance with claim 7, whereinsaid internal output signalgenerating means respectively output logical values in complementaryrelation to said logical values read from said memory cells, said logiccircuit means comprising: an output terminal, a third signal source forsupplying high-level signals, a fourth signal source for supplyinglow-level signals, a first AND circuit for outputting the logicalproduct of n-bit logical values held in said n-bit memory cellsoutputted from said internal output signal generating means of saidnumber n, a second AND circuit for outputting the logical product ofn-bit logical values in said complementary relation outputted from saidinternal output signal generating means of said number n, fifthswitching means having a control terminal connected to the output ofsaid first AND circuit, a first conducting terminal connected to saidthird signal source and a second conducting terminal connected to saidoutput terminal, and sixth switching means having a control terminalconnected to the output of said second AND circuit, a first conductingterminal connected to said fourth signal source and a second conductingterminal connected to said output terminal.
 9. A semiconductor memory inaccordance with claim 8, whereinsaid driving signal generating meanshave seventh switching means switched in response to a control signalfrom an external source of control signals to supply said drivingsignals to said memory cell writing means of said number n said memorycell function test data are being written in said memory cells and tosupply said memory cell designating signals to said memory cell writingmeans of said number n when said memory cell function test data are notbeing written into said memory cells.
 10. A semiconductor memory inaccordance with claim 7, whereinthe output of said logic circuit meansis generated through said data reading terminal.
 11. A semiconductormemory in accordance with claim 4, further comprising:a data writingterminal connected to said n-bit memory cells, designating signalgenerating means for generating memory cell designating signals fordesignating any one of said n-bit memory cells to be written with data,memory cell writing means of said number n each provided for respectiveones of said n-bit memory cells for receiving said mcmory celldesignating signals respectively from said designating signal generatingmeans thereby to write said data in said designated memory cells, anddriving signal generating means operative during a memory test mode ofoperation of said memory for generating driving signals forsimultaneously driving all of said memory cell writing means of saidnumber n to write said memory cell function test data in said memorycells.
 12. A semiconductor memory in accordance with claim 11,whereinsaid driving signal generating means are further provided withtiming signal generating means for generating timing signals to whichdata writing in said data writing terminal is synchronized whilegenerating said driving signals in response to said timing signals.